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? semiconductor components industries, llc, 2006 march, 2006 ? rev. 7 1 publication order number: mc74ac161/d mc74ac161, mc74act161, mc74ac163, mc74act163 synchronous presettable binary counter the mc74ac161/74act161 and mc74ac163/74act163 are high ? speed synchronous modulo ? 16 binary counters. they are synchronously presettable for application in programmable dividers and have two types of count enable inputs plus a terminal count output for versatility in forming synchronous multistage counters. the mc74ac161/74act161 has an asynchronous master reset input that overrides all other inputs and forces the outputs low. the mc74ac163/74act163 has a synchronous reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. ? synchronous counting and loading ? high ? speed synchronous expansion ? typical count rate of 125 mhz ? outputs source/sink 24 ma ? act161 and act163 have ttl compatible inputs these devices are available in pb ? free package(s). specifications herein apply to both standard and pb ? free devices. please see our website at www.onsemi.com for specific pb ? free orderable part numbers, or contact your local on semiconductor sales office or representative. 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 tc q 0 q 1 q 2 q 3 cet pe *r cp p 0 p 1 p 2 p 3 cep gnd figure 1. pinout: 16 ? lead packages conductors (top view) pin assignment pin function cep count enable parallel input cet count enable trickle input cp clock pulse input mr ( 161) asynchronous master reset input sr ( 163) synchronous reset input p 0 ? p 3 parallel data inputs pe parallel enable input q 0 ? q 3 flip ? flop outputs tc terminal count output http://onsemi.com dip ? 16 n suffix case 648 1 16 so ? 16 d suffix case 751b 1 16 see general marking information in the device marking section on page 11 of this data sheet. device marking information 1 16 eiaj ? 16 m suffix case 966 see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ordering information
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 2 figure 2. logic symbol *mr for 161 *sr for 163 pe p 0 p 1 p 2 cep p 3 cet cp *r q 0 q 1 q 2 q 3 tc functional description the mc74ac161/act161 and mc74ac163/act163 count modulo ? 16 binary sequence. from state 15 (hhhh) they increment to state 0 (llll). the clock inputs of all flip ? flops are driven in parallel through a clock buffer. thus all changes of the q outputs (except due to master reset of the 161) occur as a result of, and synchronous with, the low ? to ? high transition of the cp input signal. the circuits have four fundamental modes of operation, in order of precedence: asynchronous reset ( 161), synchronous reset ( 163), parallel load, count ? up and hold. five control inputs ? master reset (mr , 161), synchronous reset (sr , 163), parallel enable (pe ), count enable parallel (cep) and count enable trickle (cet) ? determine the mode of operation, as shown in the mode select table. a low signal on mr overrides all other inputs and asynchronously forces all outputs low. a low signal on sr overrides counting and parallel loading and allows all outputs to go low on the next rising edge of cp. a low signal on pe overrides counting and allows information on the parallel data (p n ) inputs to be loaded into the flip ? flops on the next rising edge of cp. with pe and mr ( 161) or sr ( 163) high, cep and cet permit counting when both are high. conversely, a low signal on either cep or cet inhibits counting. the mc74ac161/act161 and mc74ac163/act163 use d ? type edge ? triggered flip ? flops and changing the sr , pe , cep and cet inputs when the cp is in either state does not cause err ors, provided that the recommended setup and hold times, with respect to the rising edge of cp, are observed. the terminal count (tc) output is high when cet is high and counter is in state 15. to implement synchronous multistage counters, the tc outputs can be used with the cep and cet inputs in two different ways. please refer to the mc74ac568 data sheet. the tc output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip ? flops, counters or registers. logic equations: count enable = cep ? cet ? pe tc = q 0 ? q 1 ? q 2 ? q 3 ? cet mode select table *sr pe cet cep action on the rising clock edge ( ) l x x x reset (clear) h l x x load (p n q n ) h h h h count (increment) h h l x no change (hold) h h x l no change (hold) *for 163 only h = high voltage level l = low voltage level x = immaterial figure 3. state diagram 15 0 14 13 12 5 4 6 7 8 1 2 3 11 10 9
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 3 c d pe p 0 p 1 p 2 cep p 3 cet cp q 0 q 1 q 2 q 3 tc mr 161 sr 163 163 only 163 cp q 0 q 0 cp detail a detail a detail a detail a dcp d qq figure 4. logic diagram note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 161 only 161 maximum ratings* symbol parameter value unit v cc dc supply voltage (referenced to gnd) ? 0.5 to +7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature ? 65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 4 recommended operating conditions symbol parameter min typ max unit v cc supply voltage ac 2.0 5.0 6.0 v act 4.5 5.0 5.5 v in , v out dc input voltage, output voltage (ref. to gnd) 0 ? v cc v t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 3.0 v ? 150 ? v cc @ 4.5 v ? 40 ? ns/v v cc @ 5.5 v ? 25 ? t r , t f input rise and fall time (note 2) act devices except schmitt inputs v cc @ 4.5 v ? 10 ? ns/v v cc @ 5.5 v ? 8.0 ? t j junction temperature (pdip) ? ? 140 c t a operating ambient temperature range ? 40 25 85 c i oh output current ? high ? ? ? 24 ma i ol output current ? low ? ? 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times. dc characteristics symbol parameter v cc (v) 74ac 74ac unit conditions t a = +25 c t a = ? 40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 3.0 1.5 2.1 2.1 v out = 0.1 v 4.5 2.25 3.15 3.15 v or v cc ? 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 1.5 0.9 0.9 v out = 0.1 v 4.5 2.25 1.35 1.35 v or v cc ? 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 2.99 2.9 2.9 i out = ? 50 a 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v *v in = v il or v ih 3.0 ? 2.56 2.46 ? 12 ma 4.5 ? 3.86 3.76 i oh ? 24 ma 5.5 ? 4.86 4.76 ? 24 ma v ol maximum low level output voltage 3.0 0.002 0.1 0.1 i out = 50 a 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v *v in = v il or v ih 3.0 ? 0.36 0.44 12 ma 4.5 ? 0.36 0.44 i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ? 75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 5 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) symbol parameter v cc * (v) 74ac161 74ac161 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf min typ max min max f max maximum count 3.3 70 111 ? 60 ? mhz 3 ? 3 frequency 5.0 110 167 ? 95 ? t plh propagation delay 3.3 2.0 7.0 12.0 1.5 13.5 ns 3 ? 6 cp to q n (pe input high or low) 5.0 1.5 5.0 9.0 1.0 9.5 t phl propagation delay 3.3 1.5 7.0 12.0 1.5 13.0 ns 3 ? 6 cp to q n (pe input high or low) 5.0 1.5 5.0 9.5 1.5 10.0 t plh propagation delay 3.3 3.0 9.0 15.0 2.5 16.5 ns 3 ? 6 cp to tc 5.0 2.0 6.0 10.5 1.5 11.5 t phl propagation delay 3.3 3.5 8.5 14.0 2.5 15.5 ns 3 ? 6 cp to tc 5.0 2.0 6.5 11.0 2.0 11.5 t plh propagation delay 3.3 2.0 5.5 9.5 1.5 11.0 ns 3 ? 6 cet to tc 5.0 1.5 3.5 6.5 1.0 7.5 t phl propagation delay 3.3 2.5 6.5 11.0 2.0 12.5 ns 3 ? 6 cet to tc 5.0 2.0 5.0 8.5 1.5 9.5 t phl propagation delay 3.3 2.0 6.0 12.0 1.5 13.5 ns 3 ? 6 mr to q n 5.0 1.5 5.5 9.5 1.5 10.0 t phl propagation delay 3.3 3.5 10.0 15.0 3.0 17.5 ns 3 ? 6 mr to tc 5.0 2.5 8.5 13.0 2.5 13.5 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) symbol parameter v cc * (v) 74ac163 74ac163 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf min typ max min max f max maximum count 3.3 70 95 ? 60 ? mhz 3 ? 3 frequency 5.0 110 140 ? 95 ? t plh propagation delay 3.3 2.0 7.5 12.5 1.5 13.5 ns 3 ? 6 cp to q n (pe input high or low) 5.0 1.5 5.5 9.0 1.0 9.5 t phl propagation delay 3.3 1.5 8.5 12.0 1.5 13.0 ns 3 ? 6 cp to q n (pe input high or low) 5.0 1.5 6.0 9.5 1.5 10.0 t plh propagation delay 3.3 3.0 9.5 15.0 2.5 16.5 ns 3 ? 6 cp to tc 5.0 2.0 7.0 10.5 1.5 11.5 t phl propagation delay 3.3 3.5 11.0 14.0 2.5 15.5 ns 3 ? 6 cp to tc 5.0 2.0 8.0 11.0 2.0 11.5 t plh propagation delay 3.3 2.0 7.5 9.5 1.5 11.0 ns 3 ? 6 cet to tc 5.0 1.5 5.5 6.5 1.0 7.5 t phl propagation delay 3.3 2.5 8.5 11.0 2.0 12.5 ns 3 ? 6 cet to tc 5.0 2.0 6.0 8.5 1.5 9.5 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 6 ac operating requirements symbol parameter v cc * (v) 74ac161 74ac161 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf typ guaranteed minimum t s setup time, high or low 3.3 6.0 13.5 16.0 ns 3 ? 9 p n to cp 5.0 3.5 8.5 10.5 t h hold time, high or low 3.3 ? 7.0 ? 1.0 ? 0.5 ns 3 ? 9 p n to cp 5.0 ? 4.0 0 0 t s setup time, high or low 3.3 6.5 11.5 14.0 ns 3 ? 9 pe to cp 5.0 4.0 7.5 8.5 t h hold time, high or low 3.3 ? 6.0 0 0 ns 3 ? 9 pe to cp 5.0 ? 3.5 0.5 1.0 t s setup time, high or low 3.3 3.0 6.0 7.0 ns 3 ? 9 cep or cet to cp 5.0 2.0 4.5 5.0 t h hold time, high or low 3.3 ? 3.5 0 0 ns 3 ? 9 cep or cet to cp 5.0 ? 2.0 0 0.5 t w clock pulse width (load) 3.3 2.0 3.5 4.0 ns 3 ? 6 high or low 5.0 2.0 2.5 3.0 t w clock pulse width (count) 3.3 2.0 4.0 4.5 ns 3 ? 6 high or low 5.0 2.0 3.0 3.5 t w mr pulse width, low 3.3 3.0 5.5 7.5 ns 3 ? 6 5.0 2.5 4.5 6.0 t rec recovery time 3.3 ? 2.0 ? 0.5 0 ns 3 ? 9 mr to cp 5.0 ? 1.0 0 0.5 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 7 ac operating requirements symbol parameter v cc * (v) 74ac163 74ac163 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf typ guaranteed minimum t s setup time, high or low 3.3 5.5 13.5 16.0 ns 3 ? 9 p n to cp 5.0 4.0 8.5 10.5 t h hold time, high or low 3.3 ? 7.0 ? 1.0 ? 0.5 ns 3 ? 9 p n to cp 5.0 ? 5.0 0 0 t s setup time, high or low 3.3 5.5 14 16.5 ns 3 ? 9 sr to cp 5.0 4.0 9.5 11.0 t h hold time, high or low 3.3 ? 7.5 ? 1.0 ? 0.5 ns 3 ? 9 sr to cp 5.0 ? 5.5 ? 0.5 0 t s setup time, high or low 3.3 5.5 11.5 14.0 ns 3 ? 9 pe to cp 5.0 4.0 7.5 8.5 t h hold time, high or low 3.3 ? 7.5 ? 1.0 ? 0.5 ns 3 ? 9 pe to cp 5.0 ? 5.0 ? 0.5 0 t s setup time, high or low 3.3 3.5 6.0 7.0 ns 3 ? 9 cep or cet to cp 5.0 2.5 4.5 5.0 t h hold time, high or low 3.3 ? 4.5 0 0 ns 3 ? 9 cep or cet to cp 5.0 ? 3.0 0 0.5 t w clock pulse width (load) 3.3 3.0 3.5 4.0 ns 3 ? 6 high or low 5.0 2.0 2.5 3.0 t w clock pulse width (count) 3.3 3.0 4.0 4.5 ns 3 ? 6 high or low 5.0 2.0 3.0 3.5 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 8 dc characteristics symbol parameter v cc (v) 74act 74act unit conditions t a = +25 c t a = ? 40 c to +85 c typ guaranteed limits v ih minimum high level input voltage 4.5 1.5 2.0 2.0 v v out = 0.1 v 5.5 1.5 2.0 2.0 or v cc ? 0.1 v v il maximum low level input voltage 4.5 1.5 0.8 0.8 v v out = 0.1 v 5.5 1.5 0.8 0.8 or v cc ? 0.1 v v oh minimum high level output voltage 4.5 4.49 4.4 4.4 v i out = ? 50 a 5.5 5.49 5.4 5.4 *v in = v il or v ih 4.5 ? 3.86 3.76 v i oh ? 24 ma 5.5 ? 4.86 4.76 ? 24 ma v ol maximum low level output voltage 4.5 0.001 0.1 0.1 v i out = 50 a 5.5 0.001 0.1 0.1 *v in = v il or v ih 4.5 ? 0.36 0.44 v i ol 24 ma 5.5 ? 0.36 0.44 24 ma i in maximum input leakage current 5.5 ? 0.1 1.0 a v i = v cc , gnd i cct additional max. i cc /input 5.5 0.6 ? 1.5 ma v i = v cc ? 2.1 v i old ?minimum dynamic output current 5.5 ? ? 75 ma v old = 1.65 v max i ohd 5.5 ? ? ? 75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 ? 8.0 80 a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. ?maximum test duration 2.0 ms, one output loaded at a time.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 9 ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) symbol parameter v cc * (v) 74act161 74act161 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf min typ max min max f max maximum count frequency 5.0 115 125 ? 100 ? mhz 3 ? 3 t plh propagation delay cp to q n (pe input high or low) 5.0 1.5 8.0 9.5 1.5 10.5 ns 3 ? 6 t phl propagation delay cp or q n (pe input high or low) 5.0 1.5 8.0 10.5 1.5 11.5 ns 3 ? 6 t plh propagation delay cp to tc 5.0 2.0 11.0 11.0 1.5 12.5 ns 3 ? 6 t phl propagation delay cp to tc 5.0 1.5 11.0 12.5 1.5 13.5 ns 3 ? 6 t plh propagation delay cet to tc 5.0 1.5 7.5 8.5 1.5 10.0 ns 3 ? 6 t phl propagation delay cet to tc 5.0 1.5 8.0 9.5 1.5 10.5 ns 3 ? 6 t phl propagation delay mr to q n 5.0 1.5 8.0 10.0 1.5 11.0 ns 3 ? 6 t phl propagation delay mr to tc 5.0 2.5 10.0 13.5 2.0 14.5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. ac characteristics (for figures and waveforms ? see section 3 of the on semiconductor fact data book, dl138/d) symbol parameter v cc * (v) 74act163 74act163 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf min typ max min max f max maximum count frequency 5.0 120 140 ? 105 ? mhz 3 ? 3 t plh propagation delay cp to q n (pe input high or low) 5.0 1.5 5.5 10.0 1.5 11.0 ns 3 ? 6 t phl propagation delay cp to q n (pe input high or low) 5.0 1.5 6.0 11.0 1.5 12.0 ns 3 ? 6 t plh propagation delay cp to tc 5.0 2.5 7.0 11.5 2.0 13.5 ns 3 ? 6 t phl propagation delay cp to tc 5.0 3.0 8.0 13.5 2.0 15.0 ns 3 ? 6 t plh propagation delay cet to tc 5.0 2.0 5.5 9.0 1.5 10.5 ns 3 ? 6 t phl propagation delay cet to tc 5.0 2.0 6.0 10.0 2.0 11.0 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 10 ac operating requirements symbol parameter v cc * (v) 74act161 74act161 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf typ guaranteed minimum t s setup time, high or low p n to cp 5.0 7.0 9.5 11.5 ns 3 ? 9 t h hold time, high or low p n to cp 5.0 ? 3.0 0 0 ns 3 ? 9 t s setup time, high or low pe to cp 5.0 6.0 8.5 9.5 ns 3 ? 9 t h hold time, high or low pe to cp 5.0 ? 3.5 ? 0.5 ? 0.5 ns 3 ? 9 t s setup time, high or low cep or cet to cp 5.0 4.0 5.5 6.5 ns 3 ? 9 t h hold time, high or low cep or cet to cp 5.0 ? 2.0 0 0 ns 3 ? 9 t w clock pulse width (load) high or low 5.0 2.0 3.0 3.5 ns 3 ? 6 t w clock pulse width (count) high or low 5.0 2.0 3.0 3.5 ns 3 ? 6 t w mr pulse width, low 5.0 3.0 3.0 7.5 ns 3 ? 6 t rec recovery time mr to cp 5.0 0 0 0.5 ns 3 ? 9 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 11 ac operating requirements symbol parameter v cc * (v) 74act163 74act163 unit fig. no. t a = +25 c c l = 50 pf t a = ? 40 c to +85 c c l = 50 pf typ guaranteed minimum t s setup time, high or low p n to cp 5.0 4.0 10.0 12.0 ns 3 ? 9 t h hold time, high or low p n to cp 5.0 ? 5.0 0.5 0.5 ns 3 ? 9 t s setup time, high or low sr to cp 5.0 4.0 10.0 11.5 ns 3 ? 9 t h hold time, high or low sr to cp 5.0 ? 5.5 ? 0.5 ? 0.5 ns 3 ? 9 t s setup time, high or low pe to cp 5.0 4.0 8.5 10.5 ns 3 ? 9 t h hold time, high or low pe to cp 5.0 ? 5.5 ? 0.5 0 ns 3 ? 9 t s setup time, high or low cep or cet to cp 5.0 2.5 5.5 6.5 ns 3 ? 9 t h hold time, high or low cep or cet to cp 5.0 ? 3.0 0 0.5 ns 3 ? 9 t w clock pulse width high or low 5.0 2.0 3.5 3.5 ns 3 ? 6 t w clock pulse width (count) high or low 5.0 2.0 3.5 3.5 ns 3 ? 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 45 pf v cc = 5.0 v marking diagrams x = 1 or 3 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week ac16x awlyww mc74ac16xn awlyyww act16x awlyww mc74act16xn awlyyww dip ? 16 so ? 16 eiaj ? 16 74ac16x alyw 74act16x alyw
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 12 ordering information device package shipping mc74ac161n pdip ? 16 25 units/rail mc74act161n pdip ? 16 25 units/rail mc74ac161d soic ? 16 48 units/rail mc74ac161dr2 soic ? 16 2500 tape & reel mc74act161d soic ? 16 48 units/rail mc74act161dr2 soic ? 16 2500 tape & reel mc74ac161m eiaj ? 16 50 units/rail mc74act161mel eiaj ? 16 2000 tape & reel mc74ac163n pdip ? 16 25 units/rail mc74act163n pdip ? 16 25 units/rail mc74ac163d soic ? 16 48 units/rail mc74ac163dr2 soic ? 16 2500 tape & reel mc74act163d soic ? 16 48 units/rail mc74act163dr2 soic ? 16 2500 tape & reel mc74ac163mel eiaj ? 16 2000 tape & reel mc74act163mel eiaj ? 16 2000 tape & reel
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 13 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip ? 16 n suffix 16 pin plastic dip package case 648 ? 08 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 so ? 16 d suffix 16 pin plastic soic package case 751b ? 05 issue j
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 14 package dimensions eiaj ? 16 m suffix 16 pin plastic eiaj package case966 ? 01 issue o h e a 1 dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 0.78 ??? 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z
mc74ac161, mc74act161, mc74ac163, mc74act163 http://onsemi.com 15 notes on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 mc74ac161/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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